ECE 422 -- z-Plane Root Locus Design
Example #1
Lead Compensator -- Root Locus
Introduction
This example illustrates the root locus design process in the z-plane to obtain a discrete-time compensator. Various values of the sample period T will be used to show the effect that varying T has on closed-loop performance. The block diagram shows that the error signal is sampled by an ideal impulse sampler which models the analog-to-digital converter (A/D) that would actually be used in practice. The discrete-time output of the digital controller is reconstructed by a zero-order hold (ZOH) that models the digital-to-analog converter (D/A).
The open-loop transfer function for the continuous-time system is shown below. The closed-loop system with unity feedback and no compensation is stable with the closed-loop poles being s = -2 +/- j2.45. The settling time for the step response with this system is 2 seconds.
Specifications for the system are: (1) percent overshoot in the step response approximately 5% and (2) settling time for a step input of approximately 1 second.
Using the equations for the standard second-order system, the overshoot and settling time specifications correspond to a desired closed-loop pole location in the s-plane of s 1 = - 4 + 4j. This point will be mapped into the z-plane for each value of the sample period T. Although the given system does have the form of the standard second-order system, any compensation other than gain compensation will change the form of the system. Therefore, the performance achieved by the compensated system may not be the same as the second-order system equations would predict. In an actual design, a conservative approach to choosing the point s 1 is generally necessary.
Design #1, T = 0.05 sec
The desired closed-loop pole location is mapped into the point z 1 = 0.8024 + j0.1627. The magnitude and phase of this point are 0.8187 and 0.2 radians (11.5 deg), respectively. The number of samples per cycle of oscillation in the closed-loop step response can be obtained by dividing 2*pi by the phase of z 1 in radians. For this choice of T, there are 31.4 samples per cycle. This indicates that the response of the discrete-time system will closely approximate the response of the corresponding continuous-time system. The recommended rule-of-thumb is 8 to10 samples per cycle of oscillation for underdamped systems and 8 to 10 samples per rise time for overdamped systems.
The discrete-time model for the plant and ZOH was obtained by using the c2d function in MATLAB. The model is
The design process in discrete-time for the root locus method is the same as for continuous-time design. The only difference is in the regions of stability between the two planes. The steps in the design are shown below. A more detailed description of the design process is given in Compensator Design to Improve Transient Performance Using Root Locus.
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calculate the phase angle of the discrete-time plant model at the desired closed-loop pole location;
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calculate the phase angle of the compensator at that point that is needed to make the phase angle of the plant/compensator combination an odd integer multiple of 180 degrees;
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place the compensator zero at a suitable location that will provide an angle greater than that needed by the compensator and will not impair closed-loop stability;
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calculate the phase angle of the compensator zero at the desired closed-loop pole location;
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calculate the phase angle of the compensator pole at that point so that the total compensator will have the correct phase angle;
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calculate the distance from the desired closed-loop pole to the compensator pole necessary to provide the required phase angle for the compensator pole;
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calculate the compensator gain to provide unit magnitude for the plant/compensator combination at the desired closed-loop pole location.
The parameters calculated during the design procedure for this value of T are given in the following table. The resulting compensator is
| Parameter | Value |
| Desired closed-loop pole location z 1 | 0.8024 + j0.1627 |
| Phase of Plant at z 1 | 129.1 deg |
| Phase of Compensator at z 1 | 50.9 deg |
| Choice of compensator zero | 0.75 |
| Phase angle of compensator zero at z 1 | 72.1 deg |
| Phase angle of compensator pole at z 1 | 21.2 deg |
| Distance from z 1 to compensator pole | 0.4189 |
| Location of compensator pole | 0.3835 |
| Compensator Gain | 5.3842 |
| Closed-loop pole locations | 0.8024 + j0.1627, 0.8024 - j0.1627, 0.5343 |
The compensated root locus plot shows that z 1 is on the root locus, and the choice of compensator gain has made that point actually be a closed-loop pole. The closed-loop step response shows that the settling time specification has been satisfied. The overshoot is slightly larger than specified, but there was no conservatism built into the design and no attempt was made for this example to reduce the overshoot by varying the compensator zero location. With this choice of T, the discrete-time response is very close to the continuous-time response that would be obtained using the point s 1 as the desired closed-loop pole.
Design #2, T = 0.1 sec
The desired closed-loop pole location is mapped into the point z 2 = 0.6174 + j0.261. The magnitude and phase of this point are 0.6703 and 0.4 radians (22.9 deg), respectively. For this choice of T, there are 15.7 samples per cycle of oscillation. This indicates that the response of the discrete-time system will closely approximate the response of the corresponding continuous-time system.
The discrete-time model for the plant and ZOH was obtained by using the c2d function in MATLAB. The model is
The parameters calculated during the design procedure for this value of T are given in the following table. Note that the compensator pole and zero and the closed-loop poles have moved to the left relative to the first design. The resulting compensator is
| Parameter | Value |
| Desired closed-loop pole location z 2 | 0.6174 + j0.261 |
| Phase of Plant at z 2 | 122.8 deg |
| Phase of Compensator at z 2 | 57.2 deg |
| Choice of compensator zero | 0.6 |
| Phase angle of compensator zero at z 2 | 86.2 deg |
| Phase angle of compensator pole at z 2 | 29.0 deg |
| Distance from z 2 to compensator pole | 0.4719 |
| Location of compensator pole | 0.1455 |
| Compensator Gain | 3.8181 |
| Closed-loop pole locations | 0.6174 + j0.261, 0.6174 - j0.261 0.4132 |
The compensated root locus plot shows that z 2 is on the root locus, and the choice of compensator gain has made that point actually be a closed-loop pole. The closed-loop step response shows that the settling time specification has been satisfied. The overshoot is slightly larger than specified, just as with the previous design. However, with this choice of T, the discrete-time response is still very close to the continuous-time response that would be obtained using the point s 1 as the desired closed-loop pole.
Design #3, T = 0.5 sec
The desired closed-loop pole location is mapped into the point z 3 = -0.0563 + j 0.1231 and is now in the second quadrant of the z-plane. The magnitude and phase of this point are 0.1353 and 2 radians (114.6 deg), respectively. For this choice of T, there are only 3.1 samples per cycle of oscillation. This is well below the suggested range of 8 to 10 samples per cycle, and it indicates that the response of the discrete-time system will not be a good approximation to the response of the corresponding continuous-time system.
The discrete-time model for the plant and ZOH was obtained by using the c2d function in MATLAB. The model is
The parameters calculated during the design procedure for this value of T are given in the following table. Note that the compensator pole and zero and the closed-loop poles have moved to the left relative to the first design; the compensator pole is now in the left-half of the z-plane. The resulting compensator is
| Parameter | Value |
| Desired closed-loop pole location z 2 | -0.0563 + j 0.1231 |
| Phase of Plant at z 2 | 54.1 deg |
| Phase of Compensator at z 2 | 125.9 deg |
| Choice of compensator zero | 0.4 |
| Phase angle of compensator zero at z 2 | 164.9 deg |
| Phase angle of compensator pole at z 2 | 39.0 deg |
| Distance from z 2 to compensator pole | 0.1518 |
| Location of compensator pole | -0.2082 |
| Compensator Gain | 0.2924 |
| Closed-loop pole locations | -0.0563 + j 0.1231, -0.0563 + j 0.1231, 0.8324 |
The compensated root locus plot shows that z 3 is on the root locus, and the choice of compensator gain has made that point actually be a closed-loop pole. The closed-loop step response shows that the response is nowhere close to the continuous-time response that would be obtained using the point s 1 as the desired closed-loop pole. The magnitude of the third closed-loop pole at z = 0.8324 is much larger than the magnitude of the selected closed-loop pole at z = z 3. Thus, this third pole is dominant and yields a settling time of approximately 10.5 seconds. The response is overdamped so there is no overshoot, but the settling time is unacceptable relative to the specifications.
Even though the point s 1 was mapped into the z-plane just as with the first two designs, this choice for the sample period T is much too large to provide a response in discrete-time that would match the response predicted by the second-order equations. The value of T would need to be decreased from 0.5 seconds to achieve a satisfactory response.
Controller Implementation
The discrete-time compensator determined with any of these designs would likely be implemented as a difference equation on a digital computer or special-purpose digital signal processor. The input to the controller will be the sampled values of the error signal e(kT) and the output of the controller will be the sampled values of the control signal u(kT). Using the compensator from Design #1, the implementation equation would be
The equation shows that one previous value of the error signal and one previous value of the control signal are used to generate the current control signal. Therefore, two memory locations are needed for storing those values. The current value of the error signal is also used in computing the current value of control, so there will be some delay time between measuring the error signal and outputting the control signal due to the time required for computation.
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Lastest revision on Monday, September 13, 2004 3:01 PM
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